首页> 外国专利> Endurance improvement by sidewall nitridation of poly floating gate for nonvolatile memory devices using substrate or drain-side erase scheme

Endurance improvement by sidewall nitridation of poly floating gate for nonvolatile memory devices using substrate or drain-side erase scheme

机译:通过使用衬底或漏极侧擦除方案的非易失性存储器件的多晶硅浮栅的侧壁氮化来提高耐久性

摘要

A gate structure is disclosed with improved endurance characteristics. Source and drain regions are contained within a semiconductor region of a substrate. At least a gate stack, which is disposed over the semiconductor region, is situated between the source and drain regions. The gate stack contains a gate insulator layer formed over the semiconductor region, a conductive gate layer disposed over the gate insulator layer, a top gate stack layer disposed over the conductive gate layer. A sidewall insulator layer is disposed over sidewalls of the gate stack. Nitrogen atoms are incorporated along the conductive gate layer sidewall-sidewall insulator layer interface and along the conductive gate layer-gate insulator layer interface in the vicinity of the conductive gate layer edge.
机译:公开了具有改善的耐久性特征的栅极结构。源极和漏极区域包含在衬底的半导体区域内。至少一个设置在半导体区域上方的栅叠层位于源极和漏极区域之间。栅堆叠包括形成在半导体区域上方的栅绝缘体层,设置在栅绝缘体层上方的导电栅层,设置在导电栅层上方的顶栅堆叠层。侧壁绝缘层设置在栅极堆叠的侧壁上方。沿着导电栅极层侧壁-侧壁绝缘体层界面以及在导电栅极层边缘附近沿导电栅极层-栅极绝缘体层界面引入氮原子。

著录项

  • 公开/公告号US2005110057A1

    专利类型

  • 公开/公告日2005-05-26

    原文格式PDF

  • 申请/专利权人 SHIH WEI WANG;CHIA-DAR HSIEH;

    申请/专利号US20030718877

  • 发明设计人 SHIH WEI WANG;CHIA-DAR HSIEH;

    申请日2003-11-21

  • 分类号H01L29/76;

  • 国家 US

  • 入库时间 2022-08-21 22:25:08

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号