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Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein

机译:在其中具有量子点化合物半导体超晶格阵列的光电器件

摘要

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.
机译:形成纳米级电子和光电器件的方法包括形成其中具有半导体层和在该半导体层上的衬底绝缘层的衬底。在基板绝缘层上形成蚀刻模板,该蚀刻模板具有穿过其延伸的非光刻限定的纳米通道的第一阵列。该蚀刻模板可以包括阳极氧化的金属氧化物,例如阳极氧化的氧化铝(AAO)薄膜。然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。该选择性蚀刻步骤优选地使用蚀刻模板作为蚀刻掩模,以将纳米通道的第一阵列转移到下面的衬底绝缘层,该衬底绝缘层可以比蚀刻模板薄。然后,在第二纳米通道阵列中形成半导体纳米柱阵列。阵列中的半导体纳米柱的平均直径可以在约8nm至约50nm之间的范围内。半导体纳米柱也优选与半导体层同质外延或异质外延。

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