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Dummy delay line based DLL and method for clocking in pipeline ADC
Dummy delay line based DLL and method for clocking in pipeline ADC
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机译:基于虚拟延迟线的DLL和流水线ADC中时钟的方法
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摘要
A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point.signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).
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