首页> 外国专利> Recessed gate electrode MOS transistors having a substantially uniform channel length across a width of the recessed gate electrode and methods of forming same

Recessed gate electrode MOS transistors having a substantially uniform channel length across a width of the recessed gate electrode and methods of forming same

机译:在整个凹陷的栅电极的宽度上具有基本均匀的沟道长度的凹陷的栅电极MOS晶体管及其形成方法

摘要

A transistor can include an integrated circuit substrate including spaced apart isolation regions therein and an active region therebetween. A recess is formed in the active region and extends between the spaced apart isolation regions and has a bottom and opposing side wall ends that are defined by facing portions of the spaced apart isolation regions. An electrically insulating layer is formed on the bottom of the recess. A conductive material is formed in the recess on the electrically insulating layer to provide a gate electrode.
机译:晶体管可以包括集成电路衬底,该集成电路衬底在其中包括间隔开的隔离区域以及在它们之间的有源区域。凹部形成在有源区域中,并且在间隔开的隔离区域之间延伸,并且具有由间隔开的隔离区域的相对部分限定的底部和相对的侧壁端。在凹槽的底部上形成电绝缘层。在电绝缘层上的凹部中形成导电材料以提供栅电极。

著录项

  • 公开/公告号US6884677B2

    专利类型

  • 公开/公告日2005-04-26

    原文格式PDF

  • 申请/专利权人 JI-YOUNG KIM;

    申请/专利号US20030449640

  • 发明设计人 JI-YOUNG KIM;

    申请日2003-06-02

  • 分类号H01L21/8242;

  • 国家 US

  • 入库时间 2022-08-21 22:20:06

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