Methods of testing a digital frequency synthesizer in a programmable logic device using a reduced set of multiplier and divider values

摘要

Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.