Digital frequency multiplier with clock frequency generator - using logic and storage elements has divider for reducing number of clock pulses

摘要

A frequency multiplier is described which is built of digital elements and which produces 'n output pulses for every input pulse over a range of input frequencies, so that the multiplier 'n is easily varied. The system depends on a clock frequency considerably higher than the input frequency. This is divided by the multiplier, n, the resulting frequency still exceeding the input frequency. These two basic clocks are used in a counting-gating arrangement to produce the required multiplied output frequency.