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Self-aligned MIM capacitor process for embedded DRAM

机译:嵌入式DRAM的自对准MIM电容器工艺

摘要

A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.
机译:半导体器件包括一组电容器和沟槽。每个电容器包括第一导电材料层,介电层和第二导电材料层。介电层位于第一和第二导电材料层之间。第一导电材料层覆盖形成在绝缘层中的杯状开口的内表面。沟槽形成在绝缘层中。沟槽在组中的每个电容器之间延伸并与之交叉。介电层和第二导电材料层形成在杯状开口中的第一导电材料层上方和沟槽的内表面上方。第二导电材料层经由沟槽在该组电容器之间延伸。而且,第二导电材料层形成用于该组电容器的顶部电极。

著录项

  • 公开/公告号US6853024B1

    专利类型

  • 公开/公告日2005-02-08

    原文格式PDF

  • 申请/专利权人 KUO-CHI TU;

    申请/专利号US20030679098

  • 发明设计人 KUO-CHI TU;

    申请日2003-10-03

  • 分类号H01L27/108;H01L29/76;H01L29/94;H01L31/119;

  • 国家 US

  • 入库时间 2022-08-21 22:18:59

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