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Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
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机译:减少存储单元中的栅极泄漏和阈值电压波动的方法和结构
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摘要
A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of the active devices. One other of the active devices couples a virtual ground to the storage node. Potentials of the power line and the virtual ground cause the plurality of active devices to be selectively operated in near subthreshold and/or superthreshold regimes in accordance with a mode of operation.
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