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COARSE DELAY TUNER CIRCUITS WITH EDGE SUPPRESSORS IN DELAY LOCKED LOOPS
COARSE DELAY TUNER CIRCUITS WITH EDGE SUPPRESSORS IN DELAY LOCKED LOOPS
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机译:延迟锁定环中带有边缘抑制器的粗延迟调谐器电路
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摘要
The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.
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