首页> 外国专利> METHOD FOR FABRICATING SEMICONDUCTOR DEVICE FOR ACCURATELY SETTING RESISTANCE VALUE OF RESISTANCE ELEMENT AND FOR SUPPRESSING UNEVENNESS IN RESISTANCE VALUE ON SURFACE OF WAFER

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE FOR ACCURATELY SETTING RESISTANCE VALUE OF RESISTANCE ELEMENT AND FOR SUPPRESSING UNEVENNESS IN RESISTANCE VALUE ON SURFACE OF WAFER

机译:制造用于精确设置电阻元件电阻值并抑制晶圆表面电阻值不均的半导体装置的方法

摘要

PURPOSE: A method for fabricating a semiconductor device is provided to set a resistance of a resistance element with high accuracy by forming the resistance element on a transistor and an isolation layer. CONSTITUTION: An isolation layer(2) is formed in a main surface of a semiconductor substrate(1). A gate insulating layer is formed on the main surface of the semiconductor substrate. A semiconductor layer is formed on the isolation insulating layer and on the gate insulating layer. A resistance element is formed on the isolation layer and a gate electrode is formed on the gate insulating film by patterning the semiconductor layer. A mask material is formed so as to cover the resistance element. A first source/drain region is formed in the main surface of the semiconductor substrate by ion-implanting first impurities of a first conductive type. A sidewall spacer is formed on a side surface of the resistance element. A second source/drain is formed by an ion implantation using second impurities of the first conductivity type. A thermal treatment is performed to activate the second impurities.
机译:目的:提供一种用于制造半导体器件的方法,以通过在晶体管和隔离层上形成电阻元件来高精度地设置电阻元件的电阻。构成:隔离层(2)形成在半导体衬底(1)的主表面中。在半导体衬底的主表面上形成栅绝缘层。半导体层形成在隔离绝缘层上和栅极绝缘层上。通过对半导体层进行构图,在隔离层上形成电阻元件,并且在栅绝缘膜上形成栅电极。形成掩模材料以覆盖电阻元件。通过离子注入第一导电类型的第一杂质,在半导体衬底的主表面中形成第一源/漏区。在电阻元件的侧面上形成有侧壁间隔物。使用第一导电类型的第二杂质通过离子注入形成第二源极/漏极。进行热处理以活化第二杂质。

著录项

  • 公开/公告号KR20040104295A

    专利类型

  • 公开/公告日2004-12-10

    原文格式PDF

  • 申请/专利权人 RENESAS TECHNOLOGY CORP.;

    申请/专利号KR20030080113

  • 发明设计人 KOMORI SHIGEKI;

    申请日2003-11-13

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:26

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