METHOD FOR FORMING GATE OXIDE LAYER OF SEMICONDUCTOR DEVICE WITH IMPROVED SURFACE MORPHOLOGY BETWEEN HIGH-VOLTAGE AND LOW-VOLTAGE GATE OXIDE LAYERS WITH DIFFERENT THICKNESS

摘要

PURPOSE: A method for forming a gate oxide layer of a semiconductor device is provided to be capable of minimizing the topology between high-voltage and low-voltage gate oxide layers with different thickness. CONSTITUTION: First, second and third insulating layers are sequentially formed on a substrate(10) defined by a low-voltage region(LVR) and a high-voltage region(HVR). The third, second and first insulating layer of the high-voltage region are sequentially removed. By first cleaning of the resultant structure, the third insulating layer of the low-voltage region is removed and the substrate of the high-voltage region is simultaneously recessed. A high-voltage gate oxide layer(18c) is formed at the high-voltage region. The second insulating layer of the low-voltage region is removed. By second cleaning of the resultant structure, the first insulating layer of the low-voltage region is removed and the high-voltage gate oxide layer is partially recessed. A low-voltage gate oxide layer(20) is formed at the low-voltage region, and the recessed high-voltage gate oxide layer is additionally oxidized.