首页> 外国专利> METHOD FOR PLANARIZING INSULATION LAYER OF CAPACITOR OF SEMICONDUCTOR DEVICE TO PREVENT EDGE OF WAFER FROM BEING LOWERED AND ELIMINATE NECESSITY OF PROCESS FOR RE-DEPOSITING INSULATION LAYER FOR FACILITATING METAL INTERCONNECTION CONTACT MASK PROCESS

METHOD FOR PLANARIZING INSULATION LAYER OF CAPACITOR OF SEMICONDUCTOR DEVICE TO PREVENT EDGE OF WAFER FROM BEING LOWERED AND ELIMINATE NECESSITY OF PROCESS FOR RE-DEPOSITING INSULATION LAYER FOR FACILITATING METAL INTERCONNECTION CONTACT MASK PROCESS

机译:一种用于减少半导体器件电容器绝缘层以防止晶片边缘的方法,并消除了重新沉积绝缘层以利于金属互连接触面工艺的过程的必要性

摘要

A kind of purpose: method, an insulating layer for shakeouing a capacitor of semiconductor device is arranged to that the edge of a chip is prevented to reduce and eliminate the necessity of the method for a redeposited insulating layer, it is used to promote a metal interconnection contact mask process, by using HTO (high-temperature oxydation) layer to replace a low temperature insulation layer as a layer insulation between a capacitor and a metal interconnection. Construction: a capacitor part (37) is formed in semi-conductive substrate (31). One HTO films are formed in semiconductor substrate, including capacitor part. HTO films are shakeout. HTO films are from 750-800 deg.C.A temperature is deposited at after planarization process is performed, remaining HTO films have 3000-4000 angstroms of a thickness.
机译:一种目的:方法是,为了防止芯片的边缘减少和消除用于再沉积绝缘层的方法的必要性,布置用于遮蔽半导体器件的电容器的绝缘层,用于促进金属。互连接触掩模工艺,通过使用HTO(高温氧化)层代替低温绝缘层作为电容器和金属互连之间的绝缘层。构造:在半导体基板(31)上形成电容器部(37)。在包括电容器部分的半导体衬底中形成一层HTO膜。 HTO电影被淘汰。 HTO薄膜的温度为750-800摄氏度。在进行平面化工艺后,会在200摄氏度下沉积温度,其余的HTO薄膜的厚度为3000-4000埃。

著录项

  • 公开/公告号KR20050000973A

    专利类型

  • 公开/公告日2005-01-06

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030041581

  • 发明设计人 KIM JOON HO;

    申请日2003-06-25

  • 分类号H01L21/8242;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:05

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