首页> 外国专利> SEMICONDUCTOR DEVICE FABRICATING METHOD FOR SIMULTANEOUSLY FORMING STORAGE NODE CONTACT HOLE AND BITLINE INSULATION LAYER SPACER TO DECREASE NUMBER OF PROCESS

SEMICONDUCTOR DEVICE FABRICATING METHOD FOR SIMULTANEOUSLY FORMING STORAGE NODE CONTACT HOLE AND BITLINE INSULATION LAYER SPACER TO DECREASE NUMBER OF PROCESS

机译:同时形成存储节点接触孔和位线绝缘层间隔以减少工序数的半导体器件制造方法

摘要

Purpose: semiconductor device, manufacturing method is for being formed simultaneously a storage node contact hole and a bit line insulating layer gasket, it is arranged to reduce number of processes, by executing an inclined etch process in terms of etching is used to form a layer insulation of a storage node contact hole and by forming an insulating layer gasket on the side wall of a bit line. Construction: a bit line (22) is formed in semi-conductive substrate (20). One dura mater is formed in bit line. One layer insulation is formed in composite structure, has dura mater. Layer insulation is selectively etched to form the storage node contact hole for exposing semiconductor substrate, when layer insulation stays in the side wall of bit line to form insulating layer gasket (24A).
机译:用途:半导体器件,其制造方法是用于同时形成存储节点接触孔和位线绝缘层垫片,其布置成减少工艺数量,通过执行倾斜蚀刻工艺就形成了蚀刻层通过在位线的侧壁上形成绝缘层衬垫来使存储节点接触孔绝缘。构造:在半导体衬底(20)中形成位线(22)。在位线中形成一个硬脑膜。一层绝缘层形成复合结构,具有硬质材料。当层绝缘停留在位线的侧壁中以形成绝缘层衬垫(24A)时,选择性地蚀刻层绝缘以形成用于暴露半导体衬底的存储节点接触孔。

著录项

  • 公开/公告号KR20050002005A

    专利类型

  • 公开/公告日2005-01-07

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030043050

  • 发明设计人 HWANG CHANG YOUN;

    申请日2003-06-30

  • 分类号H01L21/28;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:04

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号