首页> 外国专利> SEMICONDUCTOR MEMORY DEVICE WITH TAG BLOCK FOR PREVENTING DATA LOSS BY HAVING SWITCH BETWEEN GLOBAL BIT LINE SENSE AMPLIFIER AND LOCAL BIT LINE SENSE AMPLIFIER

SEMICONDUCTOR MEMORY DEVICE WITH TAG BLOCK FOR PREVENTING DATA LOSS BY HAVING SWITCH BETWEEN GLOBAL BIT LINE SENSE AMPLIFIER AND LOCAL BIT LINE SENSE AMPLIFIER

机译:具有标签块的半导体存储器,用于通过在全局位线传感器放大器和本地位线传感器放大器之间切换来防止数据丢失

摘要

PURPOSE: A semiconductor memory device with tag block is provided to prevent data loss by having switches between the global bit line sense amplifier and the local bit line sense amplifier. CONSTITUTION: A semiconductor memory device with tag block comprises basic cell blocks(720_1, 720_2, 720_3, 720_4) consisting of unit cell blocks(720_1b, 720_2b, 720_3b, 720_4b), local bit line sense amplifier(720_1a, 720_2a, 720_3a, 720_4a) being located in one side of the unit cell block, local bit line sense amplifier(720_1c, 720_2c, 720_3c, 720_4c) being located in the other side of the unit cell block; the first global bit line sense amplifier(710a) for latching the amplified data from the local bit line sense amplifier(720_1a, 720_2a, 720_3a, 720_4a); the second global bit line sense amplifier(710b) for latching the amplified data from the local bit line sense amplifier(720_1c, 720_2c, 720_3c, 720_4c); the first global bit line connecting part(730_1), the second global bit line connecting part(730_2), and the third global bit line connecting part(730_3); a control part(800) for controlling the stored data in the first global bit line sense amplifier(710a) and the second global bit line sense amplifier(710b); the first switch(S1) for switching the data between the first global bit line sense amplifier(710a) and the second local bit line sense amplifier(720_1c, 720_2c, 720_3c, 720_4c); the second switch(S2) for switching the data between the second global bit line sense amplifier(710b) and the second local bit line sense amplifier(720_1c, 720_2c, 720_3c, 720_4c).
机译:目的:提供具有标签块的半导体存储器件,以通过在全局位线读出放大器和局部位线读出放大器之间进行切换来防止数据丢失。构成:具有标签块的半导体存储器件包括基本单元块(720_1、720_2、720_3、720_4),该基本单元块由单位单元块(720_1b,720_2b,720_3b,720_4b),本地位线读出放大器(720_1a,720_2a,720_3a,720_4a )位于单位单元块的一侧,本地位线读出放大器(720_1c,720_2c,720_3c,720_4c)位于单位单元的另一侧;第一全局位线感测放大器(710a),用于锁存来自本地位线感测放大器(720_1a,720_2a,720_3a,720_4a)的放大数据;第二全局位线感测放大器(710b),用于锁存来自本地位线感测放大器(720_1c,720_2c,720_3c,720_4c)的放大数据;第一全局位线连接部分(730_1),第二全局位线连接部分(730_2)和第三全局位线连接部分(730_3);控制部分(800),用于控制在第一全局位线读出放大器(710a)和第二全局位线读出放大器(710b)中存储的数据;第一开关(S1),用于在第一全局位线感测放大器(710a)和第二本地位线感测放大器(720_1c,720_2c,720_3c,720_4c)之间切换数据;第二开关(S2)用于在第二全局位线感测放大器(710b)和第二本地位线感测放大器(720_1c,720_2c,720_3c,720_4c)之间切换数据。

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