首页> 美国卫生研究院文献>Sensors (Basel Switzerland) >A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing
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A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

机译:一个0.6 µW斩波放大器采用高效噪声的DC伺服环路和压缩反相器级以实现高效节能的生物电势传感

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摘要

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2 , the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µV . These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.
机译:为了实现用于神经和生物电势信号传感的超低功耗和低噪声仪表放大器(IA),我们研究了两种设计技术。第一种技术使用了高噪声效率的DC伺服环路(DSL),该环路已被证明是造成高噪声的因素。所提出的方法具有几个优点:(i)电极偏移和输入偏移都被拒绝,(ii)DSL中不需要大电容,(iii)通过消除电荷分配效应,输入参考噪声(降低了IRN),(iv)通过第一级的增益和跨导比进一步降低了DSL的噪声,并且(v)提出的DSL允许与压缩反相器(SQI)级接口。所提出的技术将DSL的噪声降低到总噪声的12.5%。第二种技术是使用SQI阶段优化噪声性能。由于SQI级以2的饱和极限偏置,因此可以增加偏置电流以降低噪声,同时保持低功耗。使用共享共模反馈(CMFB)环路解决了在SQI阶段处理不匹配的难题,该环路实现了105 dB的共模抑制比(CMRR)。利用所提出的技术,采用0.18 µm CMOS工艺制造了电容耦合斩波仪表放大器(CCIA)。 CCIA的测量结果显示相对较低的噪声密度为88 nV / rtHz,积分噪声为1.5 µV。这些结果对应于5.9的有利噪声效率因子(NEF)和11.4的功率效率因子(PEF)。

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