首页> 外国专利> SELECTIVE ETCH PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC OF HIGH DIELECTRIC VALUE TO PREVENT GATE ELECTRODE FROM BEING CONSIDERABLY LIFTED OR UNDERCUT WHILE SUBSTRATE UNDER DIELECTRIC LAYER IS NOT MEANINGFULLY DAMAGED

SELECTIVE ETCH PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC OF HIGH DIELECTRIC VALUE TO PREVENT GATE ELECTRODE FROM BEING CONSIDERABLY LIFTED OR UNDERCUT WHILE SUBSTRATE UNDER DIELECTRIC LAYER IS NOT MEANINGFULLY DAMAGED

机译:用于制造具有高介电常数的栅极电介质的半导体器件的选择性蚀刻工艺,以防止栅极电介质被适当地抬起或压下,而在介质层下的基质并未完全损坏时

摘要

PURPOSE: A selective etch process for fabricating a semiconductor device with a gate dielectric of a high k value is provided to prevent a gate electrode from being considerably lifted or undercut while a substrate under a dielectric layer is not meaningfully damaged by selectively eliminating the first part of a gate dielectric layer with a high k value with respect to the second part of the gate dielectric layer of the high k value. CONSTITUTION: A gate dielectric layer(101) of a high k value is formed on a substrate. The first part(103) of the gate dielectric layer of the high k value is varied to guarantee that the first part of the gate dielectric layer with the high k value is selectively removed with respect to the second part(104) of the gate dielectric layer of the high k value.
机译:目的:提供一种选择性蚀刻工艺,用于制造具有高k值栅极电介质的半导体器件,以防止栅电极被大幅抬高或底切,同时通过有选择地去除第一部分而不会对介电层下方的衬底造成实质性损害具有高k值的栅极电介质层相对于具有高k值的栅极电介质层的第二部分的角度。组成:高k值的栅极介电层(101)形成在基板上。改变高k值的栅极电介质层的第一部分(103),以确保相对于栅极电介质的第二部分(104)有选择地去除高k值的栅极电介质层的第一部分k值高的图层。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号