SEMICONDUCTOR MEMORY DEVICE HAVING VSS/VDD BIT LINE PRECHARGE SCHEME WITH N-TYPE SENSE AMPLIFIERS AND P-TYPE SENSE AMPLIFIERS WITHOUT REFERENCE CELL

摘要

PURPOSE: A semiconductor memory device having VSS/VDD bit line precharge scheme without reference cell is provided to sense data correctly by including sense amplifiers which are two of P-type sense amplifiers for VSS precharge scheme and two of N-type sense amplifiers for VDD precharge scheme. CONSTITUTION: A semiconductor memory device comprises the first memory cell(M20); the second memory cell(M21); a bit line(BL) connected to the first memory cell(M20); a complementary bit line(BLB) connected to the second memory cell(M21); sense amplifiers for amplifying the voltage difference between the bit line and the complementary bit line. Wherein, the sense amplifiers are one of N-type sense amplifier(NS2) consisting of a pair of cross coupled NMOS transistors(NM21, NM22) and two of P-type sense amplifiers(PS20, PS21) consisting of a pair of cross coupled PMOS transistors(PM21, PM22, PM23, PM24). And the two of P-type sense amplifiers(PS20, PS21) are enabled with time lag successively.