首页> 外国专利> NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED ERASING TIME BY APPLYING THE ERASE PULSE TO WHOLE MEMORY BLOCK AS WELL AS APPLYING THE ERASE PULSE TO PARTIAL MEMORY BLOCK

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED ERASING TIME BY APPLYING THE ERASE PULSE TO WHOLE MEMORY BLOCK AS WELL AS APPLYING THE ERASE PULSE TO PARTIAL MEMORY BLOCK

机译:通过将擦除脉冲应用于全存储块以及将擦除脉冲应用于部分存储块,非易失性半导体存储器件可减少擦除时间

摘要

PURPOSE: A nonvolatile semiconductor memory device is provided to have reduced erasing time by applying the erase pulse to memory blocks up to the first erase state as well as applying the erase pulse to a partial region of the memory blocks up to the second erase state. CONSTITUTION: A nonvolatile semiconductor memory device having reduced erasing time, comprises a memory block; a select circuit for selecting an target memory for an erase pulse; and a write erase control part for controlling the data erasing when information held by the memory block is erased. Wherein, the erasing process includes the first erase state which is the midpoint of the erasing process; the second erase state which is the following state after the first erase state. And the first state and the second state exhibit a distribution of threshold voltages of plural memory transistors lower than the predetermined first and second threshold voltages, and the write erase control part controls the select circuit in order to select all memory transistors in the memory block for applying the first erase pulse repetitively until the memory block enters the first erase state, in order to supply a write pulse weaker than a write pulse of usual writing to the memory transistor when the memory block enters the first erase state(S3), and in order to divide the memory block into plural regions and supply the second erase pulse to each region until the memory block enters the second erase state(S6).
机译:用途:一种非易失性半导体存储器件,其通过将擦除脉冲施加到直到第一擦除状态的存储块以及将擦除脉冲施加到直到第二擦除状态的存储块的部分区域而具有减小的擦除时间。组成:具有减少的擦除时间的非易失性半导体存储器件,包括一个存储块;选择电路,用于选择擦除脉冲的目标存储器;写入擦除控制部分,用于控制在擦除由存储块保持的信息时的数据擦除。其中,擦除过程包括第一擦除状态,即擦除过程的中点。第二擦除状态是在第一擦除状态之后的下一状态。并且第一状态和第二状态表现出多个存储晶体管的阈值电压的分布低于预定的第一阈值电压和第二阈值电压,并且写擦除控制部分控制选择电路以便选择存储块中的所有存储晶体管以用于重复地施加第一擦除脉冲直到存储块进入第一擦除状态,以便在存储块进入第一擦除状态时向存储晶体管提供比通常写入的写入脉冲弱的写入脉冲(S3),并且为了将存储块划分为多个区域并向每个区域提供第二擦除脉冲,直到存储块进入第二擦除状态(S6)。

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