SEMICONDUCTOR INTERGRATED CIRCUIT TEST SYSTEM USING JTAG INTERFACE

摘要

The present invention relates to a test system for a semiconductor integrated circuit using the JTAG interface (Joint Test Access Group Interface). The semiconductor integrated circuit test system according to the present invention, the built-in semiconductor integrated circuit memory, is compatible with the internal memory and controls the JTAG interface, and the compatible device for generating test vectors for testing fail whether or not the built-in memory It characterized in that it comprises a control device for detecting a fail whether or not the internal memory.