首页> 外国专利> METHODS OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH THIN FILM TRANSISTORS USING A DAMASCENE TECHNIQUE AND A SELECTIVE EPITAXIAL GROWTH TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY

METHODS OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH THIN FILM TRANSISTORS USING A DAMASCENE TECHNIQUE AND A SELECTIVE EPITAXIAL GROWTH TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY

机译:利用Damascene技术和选择性表观生长技术及半导电集成电路制造具有薄膜晶体管的半导电集成电路的方法

摘要

Using a damascene technique and selective epitaxial growth techniques to provide methods and a semiconductor integrated circuit produced thereby for producing a semiconductor integrated circuit having a thin film transistor. The method are provided to as to form a single crystal semiconductor plug penetrating through the interlayer insulating layer to form a molding layer pattern for exposing the single crystal semiconductor plug on the interlayer insulating layer. It was then using the single crystal semiconductor plug in the seed layer to grow a single crystal epitaxial semiconductor pattern on the interlayer insulating layer. Sikieo planarizing the single crystal semiconductor epitaxially pattern to form a single crystal semiconductor body having a uniform thickness in the molding layer patterns. As a result, the sidewalls of the single crystal semiconductor body are becoming surrounded by the molding layer patterns, the single crystal semiconductor body has an excellent single crystal structure (single excellent crystalline structure).
机译:使用镶嵌技术和选择性外延生长技术来提供用于制造具有薄膜晶体管的半导体集成电路的方法和由此产生的半导体集成电路。提供该方法以形成穿过层间绝缘层的单晶半导体栓塞,以形成用于将单晶半导体栓塞暴露在层间绝缘层上的模制层图案。然后,使用晶种层中的单晶半导体插塞在层间绝缘层上生长单晶外延半导体图案。 Sikieo将单晶半导体外延图案平坦化,以在模制层图案中形成具有均匀厚度的单晶半导体本体。结果,单晶半导体本体的侧壁被模制层图案围绕,该单晶半导体本体具有优异的单晶结构(单优异的晶体结构)。

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