首页> 外国专利> METHODS OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH THIN FILM TRANSISTORS USING A SELECTIVE EPITAXIAL GROWTH TECHNIQUE AND A PARTIAL PLANARIZATION TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY

METHODS OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH THIN FILM TRANSISTORS USING A SELECTIVE EPITAXIAL GROWTH TECHNIQUE AND A PARTIAL PLANARIZATION TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY

机译:使用选择性表皮生长技术和局部平面化技术及半导电集成电路制造具有薄膜晶体管的半导电集成电路的方法

摘要

The selective epitaxial growth techniques and methods section, using a planarization technology for manufacturing a semiconductor integrated circuit having a thin film transistor and provides a semiconductor integrated circuit produced thereby. The method may comprises forming the insulating layer on the single crystal semiconductor substrate. Forming a single crystal semiconductor plug penetrating through the interlayer insulating layer, and forming a single-crystal semiconductor epitaxially pattern covering the interlayer insulating layer in contact with the single crystal semiconductor plug. The single crystal by patterning the semiconductor epitaxial sikieo planarize the pattern portions (partially planarizing) the inter-layer insulating layer on the semiconductor body layer to form a semiconductor body layer, to form a semiconductor body. As a result, the semiconductor body has at least is formed with a portion of the single crystal semiconductor epitaxially pattern excellent single crystal structure (single excellent crystalline structure).
机译:选择性外延生长技术和方法部分使用平面化技术来制造具有薄膜晶体管的半导体集成电路,并提供由此制造的半导体集成电路。该方法可以包括在单晶半导体衬底上形成绝缘层。形成穿过层间绝缘层的单晶半导体栓塞,并形成覆盖与该单晶半导体栓塞接触的层间绝缘层的单晶半导体外延图案。通过对半导体外延六面体进行图案化的单晶使半导体主体层上的层间绝缘层的图案部分平坦化(部分平坦化)以形成半导体主体层,从而形成半导体主体。结果,半导体主体至少具有形成有一部分单晶半导体外延图案的优异的单晶结构(单晶结构)。

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