Semiconductor memory device having circuit for screening weak cell and the screen method thereof and the arrangement method to screen weak cell

摘要

Circuitry to screen the defective cell of the semiconductor memory device, the arrangement method is disclosed for the screen and the screen method. The semiconductor memory device of the present invention comprises a memory cell, a power supply terminal, the first and the second driver unit and the cell unit power signal. A first driver section is coupled between the memory cell and a power supply terminal, in response to the cell, the power control signal is supplied to the memory cell power supply voltage. A second driver section is coupled between the memory cell and a power supply terminal, in response to a power-down signal to the cell during the test operation and supplies a predetermined voltage drop across the voltage in a memory cell power supply voltage. And cell power signal generating unit provides a power control signal and the cell-cell power-down signal. Since according to the semiconductor memory device of the present invention to a predetermined voltage drop across a power supply voltage by the cell power-down signal immediately supplied memory cells, it was needed to stabilize after a voltage change to supply a constant voltage the voltage drop in the conventional tester two hours is not required. Accordingly, the test time is reduced to the screen defective cells.