Semiconductor memory device implemented parallel bit test capable of test time and parallel bit test method using the same

摘要

PURPOSE: A semiconductor memory device is provided to embody a parallel bit test capable of reducing test time and, also, a method for testing a parallel bit using the semiconductor memory device is provided. CONSTITUTION: A semiconductor memory device includes a clock generator(13), comparing portion(20), and a parallel driver portion(30). The clock generator generates respectively the first clock pulse in response to an ascending section of a clock and the second clock pulse in response to a descending section of the clock and generates respectively the first parallel test clock in response to the first clock pulse and the second parallel test clock in response to the second clock pulse during a test order indicating a parallel bit test. The comparing portion compares data of the memory cells from first and second groups of the memory cells which are respectively synchronized to the first and second clock pulses to read. The parallel driver portion respectively transmits a logical sum of outputs of the comparing devices being connected to the first group in response to the first parallel test clock and a logical sum of outputs of the comparing devices being connected to the second group in response to the second parallel test clock to a data output terminal.