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PARALLEL BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCESSING INNER DATA AND PARALLEL BIT TEST METHOD THEREOF
PARALLEL BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCESSING INNER DATA AND PARALLEL BIT TEST METHOD THEREOF
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机译:具有访问内部数据能力的半导体存储器的并行位测试电路及其并行位测试方法
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摘要
An embodiment is a circuit including 2n-1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n-1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n-2 second comparators generate a second result by comparing signals output from some of the 2n-1 first switching circuits. N may be a natural number greater than or equal to three.
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