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Storage controller, data cache controller, a central processing unit, storage device control method, cache control method and data cache control method

机译:存储控制器,数据高速缓存控制器,中央处理单元,存储设备控制方法,高速缓存控制方法和数据高速缓存控制方法

摘要

A central processing unit having a plurality of sets of primary data cache device and the instruction processor to execute multiple threads concurrently, with a second cache unit is shared by the primary data cache device set of said plurality of physical address There is performed MI request to the secondary cache unit when the thread ID is different even if a cache line matching is registered in the cache memory, and executes the MO / BI is based on a request from the secondary cache unit the primary data cache unit that sets the RIM flag of the fetch port Te, request to the primary cache unit to perform the MO / BI If the cache line received the MI request is registered in the primary data cache unit in a separate thread I and a secondary cache units.
机译:中央处理单元具有多组主数据缓存设备和指令处理器以同时执行多个线程,而第二缓存单元则由主数据缓存设备集合共享所述多个物理地址。当线程ID不同时,即使在缓存存储器中注册了缓存行匹配项,二级缓存单元也执行该MO / BI是基于来自二级缓存单元的请求,该一级数据缓存单元设置了RIM标志取端口Te,请求主高速缓存单元执行MO / BI如果接收到的高速缓存行的MI请求被注册在主数据高速缓存单元中的单独线程I和辅助高速缓存单元中。

著录项

  • 公开/公告号JPWO2004068361A1

    专利类型

  • 公开/公告日2006-05-25

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20040567505

  • 发明设计人 山崎 巌;

    申请日2003-01-27

  • 分类号G06F12/08;G06F12/12;G06F9/52;

  • 国家 JP

  • 入库时间 2022-08-21 21:49:13

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