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Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method
Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method
A central processing device includes a plurality of sets of instruction processors that concurrently execute a plurality of threads and primary data cache devices. A secondary cache device is shared by the primary data cache device belonging to different sets. The central processing device also includes a primary data cache unit and a secondary cache unit. The primary data cache unit makes an MI request to the secondary cache unit when a cache line with a matching physical address but a different thread identifier is registered in a cache memory, performs an MO/BI based on the request from the secondary cache unit, and sets a RIM flag of a fetch port. The secondary cache unit makes a request to the primary cache unit to perform the MO/BI when the cache line for which MI request is received is stored in the primary data cache unit by a different thread.
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