首页> 外国专利> Wafer scale integration of electroplate 3D structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding

Wafer scale integration of electroplate 3D structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding

机译:使用连续光刻,电镀牺牲层和倒装芯片键合对电镀3D结构进行晶圆级集成

摘要

Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural component is formed using standard lithographic processes and electrodeposition of a structural layer. A second sacrificial wafer is separately processed using similar lithographic and electrodeposition processes to form a corresponding second three dimensional structural component. The wafers are placed in a flip-chip bonder and aligned. Once aligned, the structural components are bonded together. The bonded wafers are then removed from the bonder and the second sacrificial wafer substrate removed. The resultant die includes a three dimensional structural component with a substantially enclosed cavity as well as MEMS and IC elements.
机译:MEMS / IC芯片上的三个三维基本封闭结构的晶圆级制造使用结构层和牺牲层的电沉积以及倒装芯片对准和键合技术的组合。第一晶片包含具有MEMS和/或IC结构的管芯。在此MEMS / IC处理过的芯片上,使用标准光刻工艺和结构层的电沉积形成第一个三维结构组件。使用类似的光刻和电沉积工艺分别处理第二牺牲晶片,以形成相应的第二三维结构组件。将晶片放置在倒装芯片键合机中并对齐。对齐后,将结构部件粘合在一起。然后从键合机中移出键合的晶片,并移出第二牺牲晶片衬底。所得的管芯包括具有基本封闭的空腔的三维结构部件以及MEMS和IC元件。

著录项

  • 公开/公告号US2006134829A1

    专利类型

  • 公开/公告日2006-06-22

    原文格式PDF

  • 申请/专利权人 MICHEL A. ROSA;ERIC PEETERS;

    申请/专利号US20040012597

  • 发明设计人 MICHEL A. ROSA;ERIC PEETERS;

    申请日2004-12-16

  • 分类号H01L21/48;H01L21/50;

  • 国家 US

  • 入库时间 2022-08-21 21:47:41

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