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FFT accelerated iterative MIMO equalizer receiver architecture

机译:FFT加速迭代MIMO均衡器接收机架构

摘要

A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(Nlog2(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.
机译:诸如CDMA MIMO接收机之类的接收机包括基于LMMSE的芯片级均衡器,该均衡器构造为实现复杂度为O(Nlog 2 (N))的FFT加速迭代算法,其中N是协方差矩阵的维数。均衡器使用重叠保存或重叠相加FFT架构之一。

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