Verilog HDL simulation model for retain time

摘要

A computer program product for making a machine simulating the behavior of retain and access time of output bus is presented. The computer program product can make a simulator for detecting the transition of an input/bidirectional pin. In the retain time of the related output bus, the simulator sets a variable on in a non-blocking way, and assigns a value to a register of the output bus in a non-blocking way, wherein the value is assigned upon the transition of the input/bidirectional pin. After the retain time, the simulator sets a variable off in a blocking way, assigns the related output bus unknown in a blocking way, assigns the related output bus the value stored in the register in a non-blocking way, and sets the variable on in a non-blocking way.