Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device

摘要

To prevent the potential inversion of a dynamic node attributed to the fact that any wiring line among standard cells as is made of a wiring layer at the same level as that of the dynamic node within a standard cell is laid in adjacency to the dynamic node. ;In adjacency to a dynamic node 101 within a standard cell, shield wiring lines 102a and 102b which are made of wiring layers at the same level as that of the dynamic node are laid so as to prevent any wiring line among standard cells from passing in adjacency to the dynamic node. The shield wiring lines can be replaced with a shield region or a wiring inhibition region.