Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate

摘要

A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.