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Integrated semiconductor memory with a selection transistor formed at a ridge

机译:具有在脊处形成的选择晶体管的集成半导体存储器

摘要

An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.
机译:公开了一种具有选择晶体管的集成半导体存储器,该选择晶体管可以形成在相应的脊处。脊可以布置在绝缘层上。在脊中,第一源/漏区可以形成在脊的一个横向端,而第二源/漏区可以形成在脊的另一个的横向端。脊的纵向侧和脊的顶侧可以覆盖有包括栅电介质和栅电极的层堆叠。在选择晶体管的导通状态下可以实现高写-读电流,并且可以减小在截止状态下发生的泄漏电流。

著录项

  • 公开/公告号US6992345B2

    专利类型

  • 公开/公告日2006-01-31

    原文格式PDF

  • 申请/专利权人 GERHARD ENDERS;ANDREAS SPITZER;

    申请/专利号US20030727595

  • 发明设计人 GERHARD ENDERS;ANDREAS SPITZER;

    申请日2003-12-05

  • 分类号H01L27/108;

  • 国家 US

  • 入库时间 2022-08-21 21:41:30

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