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SEMICONDUCTOR DEVICE EXAMINING METHOD, ITS EXAMINING DEVICE, AND SEMICONDUCTOR DEVICE SUITED TO THE EXAMINATION

机译:半导体装置的检查方法,其检查装置以及适用于该检查的半导体装置

摘要

A method for examining the results after the manufacturing process of an LSI (Large scale integration) device, particularly, an examining method used for quickly and accurately examining the cross section fine structure of an LSI device produced after the manufacturing process. Its examining device and a semiconductor device suited to the examination are also disclosed. The examining method is characterized by comprising a sample making step of thinning a semiconductor chip in such a way that the substrate crystal and a portion added in the manufacturing process are included, a step of applying an electron beam to the semiconductor chip, a step of detecting an electron beam passing through the semiconductor chip to create an electron beam diffraction image, a step of removing the electron beam diffracted by the substrate crystal, and a step of comparing the lattice fringes obtained from the substrate crystal with the thickness of the portion added in the manufacturing process.
机译:一种用于在LSI(大规模集成电路)器件的制造过程之后检查结果的方法,特别是一种用于快速且准确地检查在制造过程之后制造的LSI器件的截面精细结构的检查方法。还公开了其检查装置和适于检查的半导体装置。该检查方法的特征在于,包括以使基板晶体和在制造过程中添加的部分包括在内的方式使半导体芯片变薄的样品制作步骤,向半导体芯片施加电子束的步骤,检测穿过半导体芯片的电子束以产生电子束衍射图像,去除由基体晶体衍射的电子束的步骤,以及比较由基体晶体获得的晶格条纹与添加部分的厚度的步骤在制造过程中。

著录项

  • 公开/公告号WO2006011185A1

    专利类型

  • 公开/公告日2006-02-02

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;ISHII TOSHIYA;ANDO KOKI;

    申请/专利号WO2004JP10485

  • 发明设计人 ISHII TOSHIYA;ANDO KOKI;

    申请日2004-07-23

  • 分类号G01B15/02;G01N23/225;H01J37/26;H01L21/66;

  • 国家 WO

  • 入库时间 2022-08-21 21:32:46

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