A FRACTIONAL AND INTEGER PURE DIGITAL PROGRAMMABLE CLOCK GENERATOR

摘要

An apparatus and method for generating local clock signals (298) from system clock signals (205) based upon user inputs that provide a frequency multiplier and a frequency divider (297). The frequency multiplier and frequency divider are stored in an interface (200). System Clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.