首页> 外国专利> 2-BIT SONOS TYPE MEMORY CELL COMPRISING RECESSED CHANNEL AND MANUFACTURING METHOD FOR THE SAME

2-BIT SONOS TYPE MEMORY CELL COMPRISING RECESSED CHANNEL AND MANUFACTURING METHOD FOR THE SAME

机译:包括后置信道的2bit SONOS型存储单元及其制造方法

摘要

It discloses a 2-bit SONOS type memory cell and its manufacturing method having a recessed channel. The 2-bit SONOS type memory cell in accordance with one embodiment of the invention is spaced apart by the trench is formed in a semiconductor substrate, a trench with a predetermined interval in which the first depth so as to have a second depth smaller than the first depth of the trench amounts is formed on the semiconductor substrate, the source / drain regions in the side, of the pair is formed on the semiconductor substrate between the gate oxide film, a trench is formed on the inner wall of the trench with the source / drain regions a first dielectric pattern, the first dielectric the charge trapping of the pair is formed on the pattern pattern, a charge trapping pattern image is formed in the pair of second dielectric pattern and the first dielectric pattern of the trench interior and a pair on the gate oxide film, a charge trapping pattern and the second dielectric It comprises a space and a gate formed on the second dielectric pattern between the patterns.
机译:它公开了一种具有凹入通道的2位SONOS型存储单元及其制造方法。根据本发明的一个实施例的2位SONOS型存储单元由在半导体衬底中形成的沟槽间隔开,该沟槽具有预定间隔,其中第一深度小于第二深度,第二深度小于第一深度。在半导体衬底上形成沟槽量的第一深度,在栅极氧化膜之间的半导体衬底上形成一对中的源/漏区的侧面,在沟槽的内壁上形成沟槽。源极/漏极区具有第一电介质图案,第一电介质对中的电荷俘获形成在图案图案上,电荷俘获图案图像形成在一对第二电介质图案和沟槽内部的第一电介质图案中,并且栅极氧化物膜上的电荷对图案,电荷俘获图案和第二电介质对在其间包括空间和形成在第二电介质图案上的栅极。

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