首页> 外国专利> 2-bit SONOS type memory cell comprising recessed channel and manufacturing method for the same

2-bit SONOS type memory cell comprising recessed channel and manufacturing method for the same

机译:包括凹陷通道的2位SONOS型存储单元及其制造方法

摘要

The recessed channel having a 2-bit SONOS memory cell and initiates its manufacturing method . 2-bit SONOS type memory cell is a semiconductor substrate is formed with a trench having a first depth, trench and the trench is spaced a predetermined distance so as to have a second depth smaller than the first depth amount according to an embodiment of the present invention source / drain regions formed in the semiconductor substrate next to the gate, which is formed on the inner wall of the trench oxide film, a trench with the source / drain of the pair is formed on a semiconductor substrate region between the first dielectric pattern, the first dielectric Pattern 1 is formed on the pair of the charge trapping pattern, a charge trapping pattern the second of the pair, which is formed on the dielectric pattern and the gate trench and a pair of the first pattern on the dielectric oxide film, a charge trapping pattern and the second dielectric the space between the pattern and the second comprises a gate formed on the dielectric pattern.
机译:具有2位SONOS存储器单元的嵌入式通道并启动了其制造方法。 2位SONOS型存储单元是根据本发明实施例的形成有具有第一深度的沟槽的半导体衬底,该沟槽与沟槽间隔预定距离以便具有小于第一深度量的第二深度。在形成于沟槽氧化膜的内壁上的靠近栅极的半导体衬底中形成本发明的源极/漏极区域,在第一电介质图案之间的半导体衬底区域上形成具有一对源极/漏极的沟槽。然后,在一对电荷俘获图案上形成第一电介质图案1,在第二对电荷俘获图案上形成电荷俘获图案,该第二电荷捕获图案形成在电介质图案和栅极沟槽上,并且在第一对图案上形成第一电介质氧化物膜电荷捕获图案和第二电介质位于图案与第二电介质之间的空间包括形成在电介质图案上的栅极。

著录项

  • 公开/公告号KR100546409B1

    专利类型

  • 公开/公告日2006-01-26

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20040033072

  • 发明设计人 조은석;허성회;조명관;

    申请日2004-05-11

  • 分类号H01L27/115;

  • 国家 KR

  • 入库时间 2022-08-21 21:24:22

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