首页> 外国专利> FLASH MEMORY HAVING CIRCUIT FOR AVOIDING BAD BLOCK AND METHOD OF ADDRESS-SHIFTING THEREFOR

FLASH MEMORY HAVING CIRCUIT FOR AVOIDING BAD BLOCK AND METHOD OF ADDRESS-SHIFTING THEREFOR

机译:具有避免坏块的闪存存储器的电路及其地址转换方法

摘要

A flash memory having a bad block avoidance circuit and an address shifting method therefor are disclosed. The flash memory controller for controlling the operation of the memory; A Y-buffer latch and decoder for latching and decoding address signals under control of the controller to control bit lines of a memory cell array; An X-buffer latch for latching an address signal for controlling a word line of the memory cell array under control of the controller; A block redundancy fuse unit which stores bad block information of the memory cell array, receives block address information from the X-buffer latch, combines with bad block information, and shifts the block address; And receiving data from an I / O buffer and a latch to a page-buffer to write data to a memory cell selected by the Y-buffer latch and decoder and the block redundancy fuse according to an output signal of the controller. Or a Y-gating circuit for outputting data of the page-buffer sensed from the selected memory cell to the I / O buffer and the latch.
机译:公开了一种具有不良块避免电路的闪存及其地址移位方法。闪存控制器用于控制存储器的操作; Y缓冲器锁存器和解码器,用于在控制器的控制下锁存和解码地址信号,以控制存储单元阵列的位线; X缓冲器锁存器,用于在控制器的控制下锁存用于控制存储单元阵列的字线的地址信号;块冗余熔丝单元,其存储存储器单元阵列的坏块信息,从X缓冲器锁存器接收块地址信息,与坏块信息组合,并移位该块地址;并且从I / O缓冲器和锁存器接收数据到页缓冲器,以根据控制器的输出信号将数据写入由Y缓冲器锁存器和解码器以及块冗余熔丝选择的存储单元。或Y选通电路,用于将从选择的存储单元感测到的页面缓冲器的数据输出到I / O缓冲器和锁存器。

著录项

  • 公开/公告号KR100536491B1

    专利类型

  • 公开/公告日2005-12-07

    原文格式PDF

  • 申请/专利权人 TERRA SEMICONDUCTOR INC.;

    申请/专利号KR20040049114

  • 发明设计人 LEE JONG OH;YOO SUNG JIN;HWANG TAE SUN;

    申请日2004-06-28

  • 分类号G11C16/08;G11C16/06;

  • 国家 KR

  • 入库时间 2022-08-21 21:27:15

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