Prediction methods for large-scale circuits in the presence of IP blocks.

摘要

Computer-aided design flow is experiencing the trend of combining front-end floor-planning and back-end physical placement, which is indeed necessary to achieve more efficient designs. In this process, a fast and yet accurate estimation of system parameters such as power, clock frequency, and wirelength is critical to provide the front-end tool with accurate-enough information to adjust the early design decisions before proceeding deep in the design flow.;Since clock frequency, power consumption, and chip size are largely affected by interconnect lengths, total wirelength is frequently used as a measure of quality of the placement and routing.;With the increasing size and sophistication of circuits, and specifically in the presence of IP blocks, new wirelength prediction methods are needed in the design flow of large-scale circuits. Up to now, wirelength estimation methods either did not consider IP blocks into effect, or estimated wirelength in a flat framework based on the geometrical structure of the chip area in the presence of IP blocks. In this presentation, a new estimation approach is presented for hierarchical derivation of wirelength for large-scale circuits in the presence of IP blocks using Rent's parameter of the circuit. The results are compared with another wirelength estimation method and also the actual wirelength after the placement and routing using a commercial CAD tool. It shows that the proposed technique can accurately estimate the wirelength with more than 100% improvement over its counterpart for large-scale circuits. Moreover, a study on the mutual effect of congestion and wirelength is presented.;Furthermore, Based on the proposed wirelength estimation method, a novel stochastic pre-placement approach is presented for hierarchical concurrent wirelength and congestion estimation using Rent's exponent of the circuit. The experiments illustrate that the proposed method can quickly and accurately estimate wirelength and congestion. Based on our congestion estimation method, two congestion alleviation techniques are presented. It is shown that in the presence of IP blocks using these congestion removal techniques results in 12.8% decrease in the overflow on average.;These methods are all embedded into a hierarchical well-known academic placement tool, namely Dragon which has been developed in Embedded and Reconfigurable System Design Lab in UCLA. In order to verify our theoretical results, on the real-world circuits, we picked most of our benchmarks from the ISPD placement benchmarks. For routing our benchmarks, we used the Magma Blast Fusion router which is a commercial CAD tool designed by Magma Design Automation Incorporation. The stability of our approach has been studied by using other placement tools in our flow.