首页> 外国专利> CAPACITIVELY COUPLED JUNCTION FINFET(FIN FIELD EFFECT TRANSISTOR), METHOD OF MANUFACTURING FOR THE SAME AND CMOS(COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) TRANSISTOR EMPLOYING THE SAME

CAPACITIVELY COUPLED JUNCTION FINFET(FIN FIELD EFFECT TRANSISTOR), METHOD OF MANUFACTURING FOR THE SAME AND CMOS(COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) TRANSISTOR EMPLOYING THE SAME

机译:电容耦合结型场效应晶体管(FIN场效应晶体管),其制造方法以及采用该器件的CMOS(互补金属氧化物半导体)晶体管

摘要

the capacitive coupling of the pin junction field effect transistor , a method of manufacturing the same , and relates them to the complementary transistor is employed to , and projecting from the substrate extending in a first direction transverse to the board , the pin including a first type of impurity is doped with a lower region and an upper region with the first type impurity is doped in a second, different type body and extending in a second direction perpendicular to the first direction to the gate insulating film formed on the surface of the body and the pin , and a gate electrode formed on the gate insulating film . Thus, to reduce the disadvantage of the leakage current of the junction field-effect transfection registry and secure the margins of the gate insulating film thickness of the high integration of the semiconductor device .
机译:销结型场效应晶体管的电容耦合及其制造方法及其与互补晶体管的关系,用于并沿垂直于板的第一方向延伸的衬底从衬底上伸出,所述销包括第一类;在第二不同类型的主体中掺杂第一区域杂质的下部区域,在第一区域中掺杂第一区域杂质的上部区域,并且在垂直于第一方向的第二方向上向形成在主体表面上的栅极绝缘膜延伸。该引脚以及在栅极绝缘膜上形成的栅电极。因此,减少了结型场效应转染注册表的漏电流的缺点,并确保了半导体器件的高集成度的栅极绝缘膜厚度的裕度。

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