A data transmission system, in order to synchronously with a system clock data to transmitted and a synchronous semiconductor memory

摘要

The synchronous memory device includes a data transfer control circuit (301) including a pipeline control circuit (301) which, when serial access is started in a cycle corresponding to two cycles of a clock BCK, does not separate all of the first to third pipeline stages (S1, S2, S3) from each other and brings the first pipeline stage (S1) and the second pipeline stage (S2) into a through state. When serial access is started in a cycle departing from the two cycles of the clock BCK, the pipeline control circuit (301) separates all of the first to third pipeline stages (S1, S2, S3) from each other.