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Scan path test point insertion technique scalable
Scan path test point insertion technique scalable
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机译:扫描路径测试点插入技术可扩展
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摘要
Logic circuit, and a delay fault circuit inputs and one output at least one. And standard scan of the first, the combination test point is positioned immediately after the standard scan of the first in the scan chain, delay fault circuit, the second is positioned immediately after the combination of test points in the scan chain I have a standard scan of 2.
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