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Scalable scan-path test point insertion technique
Scalable scan-path test point insertion technique
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机译:可扩展的扫描路径测试点插入技术
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摘要
A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.
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