Inverter of the SOI structure single event resistance, NAND element, NOR element, a semiconductor memory device, and data latch circuit

摘要

I will provide the inverter with a high single-event tolerance, NAND element, NOR element, memory element, the data latch circuit. Single event tolerant inverter (3I) is to (3P1,3P2,3N1,3N2) dual structure that is connected in series further transistors of the same conductivity type for each of the n-channel MOS transistor and a p-channel MOS transistor constituting the inverter , I want to connect in the connection lines between nodes of the p-channel MOS transistor of the two (A), a node between the n-channel MOS transistor of the two and (B). Data latch circuit memory element and a single event resistance (4), including (3I) the single event tolerant inverter.