首页> 外国专利> Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and method of formation

Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and method of formation

机译:减少势垒光电二极管/栅极器件的结构,以实现高效率的电荷转移和减少滞后,以及形成方法

摘要

A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.
机译:公开了一种像素单元及其形成方法,该像素单元在栅极和光电二极管彼此紧邻的区域附近具有减小的势垒。本发明的实施例提供了一种包括基板的像素单元。晶体管的栅极至少部分地形成在基板的表面下方,并且光电二极管与该栅极相邻。该光电二极管包括第一导电类型的掺杂表面层和在该掺杂表面层下面的第二导电类型的掺杂区域。掺杂的表面层至少部分地在栅极的底部的水平上方。

著录项

  • 公开/公告号US2007072333A1

    专利类型

  • 公开/公告日2007-03-29

    原文格式PDF

  • 申请/专利权人 CHANDRA MOULI;HOWARD E. RHODES;

    申请/专利号US20060582373

  • 发明设计人 CHANDRA MOULI;HOWARD E. RHODES;

    申请日2006-10-18

  • 分类号H01L21/00;

  • 国家 US

  • 入库时间 2022-08-21 21:03:18

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