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Structures and methods for implementing ternary adders/subtractors in programmable logic devices
Structures and methods for implementing ternary adders/subtractors in programmable logic devices
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机译:在可编程逻辑器件中实现三进制加法器/减法器的结构和方法
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摘要
Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.
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机译: 转换术语± Sup> [n i Sub>] f(+/-) min sup>的条件最小化结构的逻辑动态过程的方法Sub> AND ± Sup> [m i Sub>] f(+/-) min Sub>在功能添加结构中± Sup> f < Sub> 1 Sub>(Σ RU Sub>) min Sub>,不带纹波f 1 Sub>(± Sup>←←)和循环ΔtΣ Sub>→5∙f(&)-和5个条件逻辑函数f(&)-,并通过三元数系统的算术公理同时转换术语参数的过程f RU Sub>(+ 1,0,-1)及其实现其的功能结构(俄罗斯逻辑版本)