首页> 外国专利> FUNCTIONAL STRUCTURE OF ADDER f2CD) OF CONDITIONAL 'k' BIT OF PARALLEL-SERIAL MULTIPLIER fΣCD), IMPLEMENTING PROCEDURE FOR 'DECRYPTION' OF INPUT STRUCTURES OF ARGUMENTS OF TERMS 1,2Sjh1f(2n) AND 1,2Sjh2f(2n) OF 'COMPLEMENTARY CODE RU' POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC)

FUNCTIONAL STRUCTURE OF ADDER f2CD) OF CONDITIONAL 'k' BIT OF PARALLEL-SERIAL MULTIPLIER fΣCD), IMPLEMENTING PROCEDURE FOR 'DECRYPTION' OF INPUT STRUCTURES OF ARGUMENTS OF TERMS 1,2Sjh1f(2n) AND 1,2Sjh2f(2n) OF 'COMPLEMENTARY CODE RU' POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC)

机译:f (Σ CD)的条件“ k”位的条件f 2 (Σ CD )的加法器的功能结构),术语“ [ 1,2 S j h1 ] f(“的输入结构的”解密“的实现过程2 n )和[ 1,2 S j h2 ] f(2 n )通过使用三进制数系统f(+ 1,0,-1)的算术公理和逻辑微分d 1 / dn→f 1 的“互补码RU”位置格式Sub>( + ←↓- d / dn 组合结构中的参数(俄罗斯逻辑版本)

摘要

FIELD: information technology.;SUBSTANCE: invention relates to computer engineering and can be used when designing arithmetic units and performing arithmetic procedures of summation of positional arguments of analogue signals of terms [ni]f(2n) and [mi]f(2n) by applying the arithmetic axiom of the ternary number system f(+1,0,-1). The functional structure is realised using logic elements AND, OR.;EFFECT: faster operation.;1 cl
机译:技术领域本发明涉及计算机工程,并且可以在设计算术单元并执行对[n i ] f(2 < Sup> n )和[m i ] f(2 n )通过应用三进制数系统f(+ 1,0,- 1)。功能结构是通过使用逻辑元素AND或OR来实现的;效果:更快的运行速度; 1 cl

著录项

  • 公开/公告号RU2480817C1

    专利类型

  • 公开/公告日2013-04-27

    原文格式PDF

  • 申请/专利权人 PETRENKO LEV PETROVICH;

    申请/专利号RU20110151809

  • 发明设计人 PETRENKO LEV PETROVICH;

    申请日2011-12-20

  • 分类号G06F7/505;

  • 国家 RU

  • 入库时间 2022-08-21 16:23:02

相似文献

  • 专利
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号