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Vertical power JFET with low on-resistance for high voltage applications
Vertical power JFET with low on-resistance for high voltage applications
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机译:用于高电压应用的具有低导通电阻的垂直功率JFET
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摘要
A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P− region is disposed under the P+ region. The P− region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P− region may be disposed adjacent to a first portion of the P+ region while another P− region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.
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机译:结型场效应晶体管(JFET)具有栅极区,漏极区和源极区。具有第一导电类型的外延区设置在漏极区上方。第一导电类型是N型半导体材料。栅极区域设置在形成在外延区域中的沟槽内。 P +区域设置在外延区域内和栅极区域下方。 P +区具有与第一导电类型相反的第二导电类型的第一掺杂浓度。 P-区域位于P +区域下方。 P-区域具有第二导电类型的第二掺杂浓度,该第二掺杂浓度小于第一掺杂浓度。 P-区域可以邻近P +区域的第一部分设置,而另一个P-区域邻近P +区域的第二部分设置。 P +区可以从栅极区深注入到外延区中。
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