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Bias circuit for high-swing cascode current mirrors

机译:高摆幅共源共栅电流镜的偏置电路

摘要

A bias circuit for providing at least first and second bias signals for biasing a cascode current source and/or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source/drain terminals and a gate terminal. The first source/drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal. A first end of the first resistive element is coupled to the second source/drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor. The first source/drain terminal of the third transistor is coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor is coupled to a second end of the first resistive element, and the gate terminal of the third transistor is coupled to the first source/drain terminal of the second transistor.
机译:一种用于提供至少第一和第二偏置信号以偏置共源共栅电流源和/或共源共栅电流吸收器的偏置电路,其包括电阻元件以及第一,第二和第三晶体管,每个晶体管具有第一和第二源极/漏极端子和栅极。终奌站。第一晶体管的第一源极/漏极端子耦合到栅极端子,响应于在第一源极/漏极端子处接收到第一参考电流,在第一源极/漏极端子处产生第一偏置信号。第一电阻元件的第一端耦合到第一晶体管的第二源极/漏极端子。第二晶体管的栅极端子耦合到第一晶体管的栅极端子,响应于在第一源极/漏极端子处接收到第二参考电流,在第二晶体管的第一源极/漏极端子处产生第二偏置信号。第二个晶体管的第三晶体管的第一源极/漏极端子耦合到第二晶体管的第二源极/漏极端子,第三晶体管的第二源极/漏极端子耦合到第一电阻元件的第二端,并且栅极端子第三晶体管的漏极耦合到第二晶体管的第一源极/漏极端子。

著录项

  • 公开/公告号US7208998B2

    专利类型

  • 公开/公告日2007-04-24

    原文格式PDF

  • 申请/专利权人 CHRISTOPHER J. ABEL;

    申请/专利号US20050103813

  • 发明设计人 CHRISTOPHER J. ABEL;

    申请日2005-04-12

  • 分类号G05F1/10;G05F3/02;

  • 国家 US

  • 入库时间 2022-08-21 21:01:16

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