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Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays
Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays
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机译:用于包含随机存取存储器阵列的集成电路器件的减少的门延迟多路复用接口和输出缓冲电路
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摘要
A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.
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