GATED LATERAL THYRISTOR-BASED RANDOM ACCESS MEMORY (GLTRAM) CELLS WITH SEPARATE READ AND WRITE ACCESS TRANSISTORS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME

摘要

A memory device (340) is provided which includes a write bit line (452), a read bit line (454), and at least one memory cell (410). The memory cell (410) includes a write access transistor (470), a read access transistor (480) coupled to the read bit line (454) and to the first write access transistor (470), and a gated-lateral thyristor (GLT) device (460) coupled to the first write access transistor (470). Among its many features, the memory cell (410) prevents read disturbances during read operations by decoupling the read and write bit lines (454, 452). FIG. 4